Since the mid-1970s, the structural testing of loaded printed circuit boards (PCBs) has relied very heavily on the use of the so-called in-circuit “bed-of-nails” technique (FIG. 1). This method of testing makes use of a fixture containing a bed-of-nails to access individual devices on the board through test lands laid into the copper interconnect, or other convenient contact points. Testing then generally proceeds in two phases: the power-off tests followed by power-on tests.
Power-off tests check the integrity of the physical contact between nail and the on-board access point. They then may carry out open and shorts tests based on impedance measurements. Power-on tests apply stimulus to a chosen device on a board, with an accompanying measurement of the response from that device. Other devices that are electrically connected to the device-under-test are usually placed into a safe state (a process called “guarding”). In this way, the tester is able to check the presence, orientation, and bonding of the device-under-test in place on the board.
Fundamentally, the in-circuit bed-of-nails technique relies on physical access to all devices on a board. For plated-through-hole technology, the access is usually gained by adding test lands into the interconnects on the “B” side of the board—that is, the solder side of the board. The advent of surface mount devices meant that manufacturers began to place components on both sides of the board—the “A” side and the “B” side. The smaller pitch between the leads of surface-mount components caused a corresponding decrease in the physical distance between the interconnects. This had serious impact on the ability to place a nail accurately onto a target test land. The question of access was further compounded by the development of multi-layer boards.
In the 1980s a group known as the Joint Test Action Group (JTAG) examined the problem and its possible solutions. Their preferred method of solution was based on the concept of placing a series of cells forming a serial shift register, around the boundary of the device. This shift register became known as a boundary-scan register. The JTAG approach ultimately became an international standard known as the IEEE 1149.1 “Test Access Port and Boundary-Scan Architecture”. As used herein, the terms “JTAG”, “JTAG compliant”, and/or “IEEE 1149.1” are interchangeably used to refer to this standard (including subsequent revisions and modifications thereof) and/or devices that are compliant with this standard.
The boundary-scan cells forming the boundary-scan register essentially formed a series of “virtual nails”, which may be used in a manner similar to the actual nails discussed above to test the presence, orientation, and bonding of devices in place on a board. In particular, the prime function of the bed-of-nails in-circuit tester, and thus, the boundary-scan architecture, has been to test for manufacturing defects, such as missing devices, damaged devices, open and short circuits, misaligned devices, and wrong devices.
It was assumed that devices had already been tested for functionality when they existed only as devices (i.e., prior to assembly on the board). Boundary-scan architecture was viewed as an alternative way of testing for the presence of manufacturing defects, including defects caused by shock, such as electrical shock (e.g., electrostatic discharge), mechanical shock (e.g., clumsy handling), or thermal shock (e.g., hot spots caused by the solder operation). A defect, if it occurs, is likely present either in the periphery of the device (leg, bond wire, driver amplifier), in the solder, or in the interconnect between devices. It is very unusual to find damage to the core logic without there being some associated damage to the periphery of the device. In-circuit testers thus generally were not configured or intended to prove the overall functionality of the devices.
However, with the proliferation of complex board mounted systems, it is often desirable to effect in-depth testing of individual components. A need thus exists for a method and apparatus for emulating and/or debugging individual devices using existing scan chain architecture.